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The present invention relates generally to application-specific integrated circuit (ASIC) design. More specifically, but without limitation thereto, the present invention relates to a method for generating a cell function and timing model in a standard library format for a specific technology from a cell design description.
Application-specific integrated circuit (ASIC) design tools are used to simulate a circuit design to detect and solve design problems until the design goals are achieved in theory before committing to the expense of physically manufacturing the ASIC. Current design methods require manually developing a cell timing model for a specific technology in a standard format for third party ASIC design software such as a Verilog model library. To migrate a circuit design to a new technology requires manually updating the Verilog model library. The manual effort required for developing and updating cell timing models is time-consuming and prone to introducing errors.
The present invention advantageously addresses the problems above as well as other problems by providing a method for automatically generating a standard cell timing model library from a technology-independent functional description.
In one embodiment, the present invention may be characterized as a method of generating a cell function and timing model library in a standard library format that includes the steps of (a) receiving as input a model source file, a technology dependent file, and a cell list data file; (b) parsing a functional description for each cell in the cell list data file from the model source file; (c) expanding parameterized timing data for each cell in the cell list data file from the technology dependent file; and (d) generating as output a standard cell model library from the parameterized timing data.